1. Field of the Invention
The present invention relates to a method of manufacturing a flash memory device and, more specifically, to a method of manufacturing a flash memory device that can improve effective field oxide height (hereinafter, referred to as “EFH”) variation between a cell region, a high-voltage transistor region and a low-voltage transistor region in a flash memory device using a self-aligned shallow trench isolation (hereinafter, referred to as “SA-STI”) scheme.
2. Discussion of Related Art
A flash memory is provided with a high-voltage transistor and a low-voltage transistor for driving cells in view of a device's characteristic. A gate oxide film of the high-voltage transistor has a thick thickness, a gate oxide film of the low-voltage transistor has a thin thickness, and a gate oxide film of the cell has the same or similar thickness as those of the low-voltage transistor. For example, in a 120 nm level NAND flash memory device, the gate oxide film in the cell may be about 80 Å in thickness, the gate oxide film in the high-voltage transistor may be 350 Å in thickness, and the gate oxide film in the low-voltage transistor may be about 80 Å in thickness. A difference in a topology depending on the thickness of the oxide film in each region results in EFH variation between the high-voltage transistor region and the cell region or the low-voltage transistor region after a chemical mechanical polishing (hereinafter, referred to as “CMP”) process for performing a field oxide film, a subsequent process, is performed. In the above, EFH refers to an effective height of a field oxide film that is protruded upwardly from the interface between a first polysilicon layer for a floating gate and a second polysilicon layer for a floating gate.
FIG. 1 is a cross-sectional view illustrating a method of manufacturing a flash memory device using the SA-STI scheme according to a related art.
Referring to FIG. 1, a semiconductor substrate 11 in which a cell region CELL, a high-voltage transistor region HV and a low-voltage transistor region LV are defined is provided. A high-voltage gate oxide film 12H is thickly formed on the semiconductor substrate 11 of the high-voltage transistor region HV, and a low-voltage gate oxide film 12L and a cell gate oxide film 12C are thinly formed on the semiconductor substrate 11 of each of the low-voltage transistor region LV and the cell region CELL. A first polysilicon layer 13 for a floating gate is formed on the oxide films 12C, 12H and 12L. A SA-STI process is then performed to form a number of trenches 15 for isolation in the semiconductor substrate 11. The trenches 15 are buried with oxide for isolation to form field oxide films 160. A second polysilicon layer 17 for a floating gate is then formed on the entire structure including the field oxide films 160. Though not shown in the drawing, an etch process using a mask for a floating gate, a dielectric film formation process, a process of forming a conductive layer for a control gate, and an etch process using a mask for a control gate are performed to form gates in the respective regions CELL, HV and LV.
If the flash memory device is fabricated by the above-mentioned method, however, EFH variation takes place among the field oxide films 160 each formed in the regions CELL, HV and LV due to a difference in a topology of the oxide films 12C, 12H and 12L, which are formed in the cell region CELL, the high-voltage transistor region HV and the low-voltage transistor region LV, respectively. It results in EFH variation of about 300 Å or more, even if a nitride film strip process that is used in a SA-STI process after a CMP process and a cleaning process that is performed before the second polysilicon layer 17 is deposited are performed. The EFH of the field oxide film 160 in the high-voltage transistor region HV is about 50 to 200 Å, while the EFH of the field oxide film 160 in the cell region CELL or the low-voltage transistor region LV is 300 to 800 Å. The EFH of the cell region CELL and the low-voltage transistor region LV are high and wide in value. Such values vary depending on conditions of the CMP process. Variation in the EFH between the high-voltage transistor region HV and other regions CELL and LV not only causes many problems such as making it difficult to set a gate etch target of each of the regions CELL, HV and LV, making it impossible to obtain a good gate pattern profile, causing a fail in a device due to polysilicon remnant, and the like. These problems become critical, as the devices is higher integrated. An attempt to solve these problems has been made.